1. Field of the Invention
The present invention relates to a control device of a neutral point clamped power inverter apparatus designed to generate a three-level output voltage and applied to a pulse width modulation (PWM) control converter apparatus for converting AC power into DC power, a PWM control inverter apparatus for converting DC power into AC power, and the like.
2. Description of the Related Art
In the main circuit of a conventional neutral point clamped power inverter apparatus shown in FIG. 1, reference symbols Vd1 and Vd2 denote DC power supplies; S1 to S4, self-extinction elements; D1 to D4, freewheeling diodes; D5 and D6, clamping diodes; and LOAD, a load. An output voltage Vu from this inverter apparatus changes upon ON/OFF operations of the four elements S1 to S4 in the following manner. Note that a total DC voltage Vd is represented by the following equation: EQU Vd1=Vd2=Vd/2
When the elements S1 and S2 are ON, Vu =+Vd/2.
When the elements S2 and S3 are ON, Vu =0.
When the element S3 and S4 are ON, Vu=-Vd/2.
In this case, the self-extinction elements must be turned on in pairs. If three of the elements are turned on at once, a corresponding DC power supply is short-circuited, and the elements are distracted by an overcurrent.
If, for example, ON signals are respectively input to the elements S1 to S3, the DC power supply Vd1 is short-circuited through the elements S1, S2, and S3 and the diode D6. As a result, an excessive short-circuit current flows to the elements to destruct them.
In order to prevent such a DC short circuit, the elements S1 and S3 are inversely operated, while the elements S2 and S4 are inversely operated. That is, when the element S1 is turned on, the element S3 is turned off, and vice versa. In this case, since the elements S1 and S3 are not immediately turned off upon reception of OFF gate signals, an OFF signal is kept supplied to one of the elements until the other element is completely turned off. The corresponding period of time is called an idle time, which has been considered as an indispensable factor. Similarly, when the element S2 is turned on, the element S4 is turned off with an idle time, and vice versa.
The conventional neutral point clamped power inverter apparatus, therefore, is operated in accordance with a pulse width modulation control method indicated by the timing chart shown in FIG. 2.
Referring to FIG. 2, reference symbols X and Y denote carrier signals of PWM control. The signal X is a triangular wave which changes in level between +EMAX and -EMAX. The signal Y has the inverted value of the signal X (or a triangular wave whose phase is shifted from that of the signal X by an electric angle of 180.degree.). In addition, reference symbol ei denotes a PWM control input signal.
Gate signals g1 and g2 for the elements S1 to S4 are formed by comparing the input signal ei with the triangular waves X and Y. More specifically,
If ei&gt;X and ei&gt;Y, g1=1 is formed to turn on the element S1 and turn off the element S3. PA1 If ei.ltoreq.X or ei.ltoreq.Y, g1=0 is formed to turn off the element S1 and turn on the element S3. PA1 If ei&lt;X and ei&lt;Y, g2=1 is formed to turn on the element S4 and turn off the element S2. PA1 If ei.gtoreq.X or ei.gtoreq.Y, g2=0 is formed to turn off the element S4 and turn on the element S2.
As a result, the output voltage Vu has the waveform illustrated at the lowest position in FIG. 2. In this manner, in the neutral point clamped power inverter apparatus, a voltage having a three-level (+Vd/2, 0, and -Vd/2) voltage waveform with a small amount of high-frequency components can be obtained as the output voltage Vu. When such a voltage is applied to a motor load, current pulsation can be reduced, and a reduction in torque ripple can be achieved.
The following problems, however, are posed in the above-described conventional neutral point clamped power inverter apparatus.
If the level of the input signal ei is very low, as shown in FIG. 3, the pulse width of each of the gate signals g1 and g2 is reduced. If this pulse width becomes shorter than a minimum ON time .DELTA.t of the elements S1 to S4 constituting the inverter apparatus, a problem is posed as follows.
In a large-capacity inverter apparatus, a GTO (gate turn-off) thyristor is used as a self-extinction element, and a snubber circuit for restricting an over-voltage in a turn-off period is connected to the GTO thyristor. When the GTO thyristor is turned on to initialize (discharge) the voltage of a capacitor in this snubber circuit, the ON state of the GTO thyristor must be maintained for a predetermined period of time (the minimum ON time .DELTA.t: e.g., about 100 microseconds).
In the case shown in FIG. 3, the input signal ei is decreased in level, so that the time interval during which the gate signal g1 is at "1" level, i.e., the time interval during which the element S1 is ON (the element S3 is OFF), becomes shorter than the minimum ON time .DELTA.t. Therefore, in order to secure the minimum ON time of the element, the gate signal g1 is corrected to form a signal g1' having a pulse width corresponding to the minimum ON time .DELTA.t. Similarly, the gate signal g2 is corrected to form a signal g2'. As a result, the output voltage Vu has the waveform at the lowest position in FIG. 3. Consequently, the average value Vu of output voltages is a constant positive or negative value regardless of the value of the input signal ei, as indicated by dotted lines in FIG. 3.
That is, according to the control device of the conventional neutral point clamped power inverter apparatus, when the level of the input signal ei is decreased, the output voltage Vu becomes a constant value regardless of the value of the input signal ei. This renders it impossible to control a load current Iu. Especially when an output frequency is low, voltage errors are accumulated to increase the load current Iu. In the worst case, the corresponding element is distracted.
In addition, if an abrupt change in level of the input signal ei occurs, the pulse width of the gate signal g1 is increased to secure the minimum ON time .DELTA.t of the element S1. As a result, since the gate signal g1, whose pulse width is increased, partially overlaps the gate signal g2, the element S1 is turned on, the element S2 is turned off, the element S3 is turned off, and the element S4 is turned on. Therefore, the total DC voltage Vd=Vd1+Vd2 is applied to the element S2 or S4 to destruct the element S2 or S4.
The above-described conventional problems can be summarized as follows:
a. When the level of the input signal ei is low, it is impossible to control the self-extinction elements.
b. In order to prevent a DC short circuit, an idle time is required to control each self-extinction element.
c. If an abrupt change in level of the input signal ei occurs, an overvoltage is applied to a corresponding self-extinction element, and the element is distracted.